In practice, circuit configurations for analog/digital conversion have proven prone to errors. For example, software errors may have the effect that, instead of a desired address, a wrong address is applied to the address input, and because of that, instead of a desired analog signal, a wrong analog signal is converted. Or hardware faults, such as defective lines, may appear within the circuit configuration. For these reasons, it is necessary to monitor circuit configurations for converting analog signals to digital signals.
A method for monitoring a circuit configuration for analog/digital conversion is described in German Patent Application No. DE 196 31 972 C2. In this context, a sequence of digital pulses is generated, based on an analog signal that is to be digitized, of which at least the width or the repetition frequency are dependent on the analog signal.
Subsequently, it is checked whether this pulse frequency and a digital value, generated by the circuit configuration based on the same analog signal, correspond to each other. It is true that the circuit configuration may be checked for hardware faults, but no checking takes place of the correct addressing of one of several analog signal inputs.
Methods that permit checking a circuit configuration for analog/digital conversion for correct addressing of their analog signal inputs use, for example, known analog test signals which are temporarily applied to the analog signal inputs of the circuit configuration instead of useful signals. Using the sequential application of the addresses assigned to these analog signal inputs to the address input, the test signals present at the respective analog signal inputs are digitized, one after another, by the circuit configuration. Because known signals are involved as the test signals, the result of their conversion is known per se, so that, as the result of the conversion of a respective test signal, in each case a certain digital setpoint value may be expected. If the result of the conversion of one of the test signals leads to a different setpoint value than the one that was expected, this is evaluated as being an indication of the faultiness of the circuit configuration. However, in order to carry out such checking, a change-over of the circuit configuration into a test mode is required, in which the test signals are applied, instead of the useful signals that are otherwise converted, to the inputs of the circuit configuration, so that the conversion of the useful signals has to be interrupted while the circuit configuration carries out the checking. In particular, for this reason, repeated checking may not be carried out at short time intervals, but only at relatively long time intervals between the individual tests. Furthermore, the possibility exists, in the case of such circuit configurations, that a fault is diagnosed as to whether the conversion of the useful signals is proceeding correctly, only because the switchover to the test signals is interfered with.
One possibility for removing this problem is to provide a more or less identical circuit configuration parallel to the circuit configuration that is to be monitored, in each case both configurations converting the same analog signal, and in each case digital signals generated by the two configurations being compared to each other. However, the practical implementation of such monitoring using two circuit configurations requires double the technical expenditure, and, accordingly, it is costly. In addition, such a technical approach runs counter to the general trend towards miniaturization of circuits.